Search

2 articles for “PVT”

• Published Subscription Original Research 9 Apr 2025

  DFT Compatible Low Power EDAC Based on Clock Gating

  By Hemapriya C, Sananda S, Sneha M., Suryakala S

  Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article →

• Published Subscription Review Article 31 Dec 2025

  Satellite sensing in Aero-plan guidance and radar tracking system

  By Shaikh Heena T, Kazi Kutubuddin Sayyad Liyakat

  Abstract: Satellite sensing, far from being a mere auxiliary tool, is rapidly becoming the indispensable spinal cord of modern aeroplane guidance and radar tracking systems, promising a future of unparalleled precision, efficiency, and safety. The relentless demand for safer, more efficient, and globally integrated air traffic management necessitates a continuous evolution of aeroplane guidance and radar tracking systems. This paper outlines the transformative role and study of satellite sensing, specifically Global …

  Published in International Journal of Satellite Remote Sensing · Vol. 3, Issue 2, 2025 · pp. 37–45 Read article →