Search
6 articles for “GPU accelerators”
-
Parallel Privacy-Preserving Adaptive Federated Learning on GPU-Enabled Multi-Core Architectures
Abstract: The increasing deployment of parallel and distributed intelligent systems has intensified the need for privacy-preserving learning frameworks that can exploit multi-core and GPU-based architectures without centralizing sensitive data. This work proposes a parallel Adaptive Federated Learning (AFL) framework that integrates Differential Privacy and Secure Aggregation over heterogeneous multi-core and GPU platforms to enhance both data confidentiality and convergence efficiency. The framework dynamically adjusts client participation, learning rates, and aggregation weights …
Published in Recent Trends in Parallel Computing · Vol. 13, Issue 1, 2026 Read article
-
Energy-efficient Image Classification on Edge Devices: Implementation and Evaluation
Abstract: Image classification is a computer vision problem where an algorithm determines a class or label for a given image. Various real-time applications like object recognition, medical diagnosis, person recognition, etc. Image classification property on edge devices is useful for autonomous vehicles, surveillance, and healthcare and internet of things deployments. The advancement of deep learning based methods and graphics processing units (GPU) devices allows efficient processing locally. The study utilizes a …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 11, Issue 3, 2024 · pp. 10–18 Read article
-
Design and Optimization of Domain-Specific Languages for High-Performance Computing Applications
Abstract: The accelerating demand for computational power in scientific, engineering, and data-intensive domains has driven High-Performance Computing (HPC) systems toward unprecedented levels of parallelism and architectural complexity. Contemporary HPC platforms integrate multicore CPUs, many-core GPUs, accelerators, and deep memory hierarchies, creating significant challenges for software development and performance optimization. Traditional general-purpose programming languages and parallel programming frameworks provide low-level control over hardware resources but require extensive manual tuning, resulting in poor …
Published in Recent Trends in Parallel Computing · Vol. 13, Issue 1, 2026 Read article
-
Face Recognition Attendance System Using Local Binary Pattern Histogram Algorithm
Abstract: Maintaining accurate and tamper-proof attendance records in educational and corporate environments has long been a challenge due to the limitations of manual and biometric systems. This study introduces the development and deployment of a contactless, automated attendance system that utilizes facial recognition through the local binary pattern histogram (LBPH) algorithm. The primary goal is to offer a secure and efficient substitute for conventional attendance methods by harnessing the power of …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 13, Issue 1, 2026 · pp. 29–34 Read article
-
Parallel Greedy Approach for Phylogenetic Tree Construction in the Context of Marine Species
Abstract: The rebuilding of phylogenetic trees for marine species shows major computing problems because of the massive genomic data and the huge biodiversity inherent in ocean ecosystems. Traditional phylogenetic methods are accurate but become more expensive when they are processing with thousands of marine taxa parallelly. This article shows a critical analysis of parallel greedy algorithms as an adaptable solution for large-scale marine phylogenetics. It examines the main principles of greedy …
Published in International Journal of Algorithms Design and Analysis Review · Vol. 4, Issue 1, 2026 · pp. 33–45 Read article
-
Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article