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1824 articles for “Program” (ranking capped at the first 2,000 matches — narrow the search to see the rest)
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Torsional Strengthening of RC Beam using Ferrocement Jacketing
Abstract: Due to the type of loading on the structure, it is generally known that there are four structural actions: axial force, shear, bending, and torsion. The reinforced concrete beams are said to be subjected to torsion, when the point of application of lateral loads does not coincides with shear center of the beam. These loads may be due to loading pattern or connection of beam. Torsional failure is typically seen …
Published in Journal of Structural Engineering and Management · Vol. 9, Issue 2, 2022 · pp. 13–23 Read article
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Comparison of Conventional RCC Columns, Steel Columns and Composite Columns
Abstract: Worldwide, the steel industry is expanding almost everywhere. Compared to the USA, EU, and other developed nations, India uses less steel in the construction industry. Additionally, India's cities have some of the highest population densities per square kilometre, which limits horizontal construction growth and favours vertical development. Steel structures are more ductility and can undergo more deflections while concrete structures are larger and attracts more seismic weight. Hybrid construction combines …
Published in Journal of Structural Engineering and Management · Vol. 10, Issue 3, 2023 · pp. 35–44 Read article
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Vector Signal Transceiver (VST) in LabVIEW: A Review
Abstract: AbstractOver the past few decades, the increasingly popular architecture of RF systems with software has become increasingly popular. Almost every commercial automated RF system (COTS) today uses application software for communication via the bus interface with the device. As the complexity of radio frequency applications is increasing, engineers are constantly faced with the dilemma of increasing functionality without increasing testing time and, ultimately, to verify the cost. Although improvements in …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 1–5 Read article
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Analysis of Wireless Tactical Network (WTN)
Abstract: AbstractIn the present paper the goal of the WTN program was to develop an adaptive networking capability that dramatically improved performance and reduced communication failures in complex communication networks. The past decades have witnessed advances in computing and communication technologies. Faster, smaller and more reliable devices enable communications with rapid, efficient information dissemination between mobile. These advantages are on demand setup, fault tolerance, node’s increased mobility, self-organizing connectivity, adaptive, scalable …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 6, Issue 3, 2019 · pp. 31–37 Read article
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Study and Analysis of 5G Research Activities
Abstract: This paper summarizes the key initiatives in favor of 5G wireless communication networks. Recent program and project activities and documents are highlighted. A closer examination of a series of 5G-related projects in the European Union is carried out. The literature review is limited to recent issues of IEEE Communications 5G Journal and related white papers from various sources. The aim is to shed light on what 5G is: what are …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 8, Issue 3, 2021 · pp. 18–27 Read article
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Artificial Intelligence-based Chatbot for Disease Prediction
Abstract: Nowadays leading a healthy lifestyle is very important. Sometimes it is even difficult to find proper medical consultation in unsocialized and remote areas. One such solution to these issues is the development of an Artificial Intelligence based Chatbot for Disease Prediction. A Chatbot is a software program that simulates human conversations, through AI’s Natural Language Processing (NLP) capability. A text-to-text chatbot for disease prediction can involve patients into an interactive …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 10, Issue 1, 2023 · pp. 29–36 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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Memristor based Material Implication Logic for Implementation of Basic logic Gates and Circuits
Abstract: A physical memristor was realized a few years back by Hewlett Packard labs. Instantly it became the topic of interest for many scientists and researchers. Memristor has joined resistor, capacitor and inductor in the list of basic two-terminal passive circuit elements. Field Programmable Gate Arrays (FPGAs) have become a major choice of technology for the implementation of various digital circuits because they offer various features such as quick time to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 17–22 Read article
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Optimized AES Implementation on Leon3
Abstract: This paper presents implementation of AES (Advanced Encryption Standard) on LEON3 which is a soft-core processor. We have used the AMBA (Advanced Microcontroller Bus Architecture) bus for interfacing our AES IP (Intellectual Property) core with Leon3 processor. AMBA bus is an in built open source bus which comes along with Leon3 processor. We have mainly analyzed parameters such as throughput, slice utilization and compared our model based with previous work. …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 30–33 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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Automated Access Backdoor for UVM_REG Layer
Abstract: Systems on chips (SoCs) design have many configuration registers. Configuring the registers through a Bus protocol consumes lot of simulation time. Hence, time saving becomes a challenge in configuring the registers. The other way to configure registers is backdoor access. Backdoor is a zero simulation time access by mapping to the register directly using the hierarchical path. It allows rapid configuration of registers and can uncover hidden bugs as execution …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 49–53 Read article
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Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression
Abstract: Flexible and scalable motion estimation processor for the h.264 advanced video coding standard handling the processing requirements for high-definition video and suitable for Field-Programmable Gate Array (FPGA) implementation. The new motion estimation algorithm of kalman filter used to reduce the computational complexity. The eight custom instruction sets are used in the motion estimation. All processor instances are remaining binary compatible so recompilation process is not required. The motion estimation algorithm …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 1–5 Read article
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An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator
Abstract: This paper aims at designing a Field programmable gate array (FPGA)-based proportional, integral derivative (PID) controller in a servo-actuated control system. In the conventional method of implementing control systems in FPGA, there is no interaction between the controller and the system except for the final stage of implementing control system in the hardware. The proposed methods provide approaches for analyzing the performance of the controller and system in MATLAB simulink …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 1–6 Read article
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Design of 16-bit Pipelined RISC Processor
Abstract: This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 32–37 Read article
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation
Abstract: Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 55–61 Read article
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A Differentiator Based on Second Generation Current Controlled Conveyor
Abstract: A new second generation current controlled conveyor (CCCII) with programmable gain at output terminal ‘Z’ is presented in this paper. The inherent advantages of the proposed circuits are low supply voltage requirement of ±0.85 V, small input parasitic resistance in the range of 29.12 Ω–297.71 Ω for a current range of 10 µA–300 µA, low power dissipation of 79.39 µw and low DC current error of 0.068%. The proposed CCCII …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 89–95 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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An Overview to Transmitter Device Or Gesture Device Components
Abstract: An accelerometer is an electromechanical scheme used to measure acceleration forces. Those powers may be stationary, like the nonstop force of gravity or, as is the case with many movable devices, dynamic to intellect program or vibrations. Acceleration is the capacity of the modification in velocity, or speed separated by phase. Let us take an example, a car speed up from a halt to 60 mph in six seconds is …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 3, 2019 · pp. 12–15 Read article