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1930 articles for “LeNet-5” (ranking capped at the first 2,000 matches — narrow the search to see the rest)
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Vector Signal Transceiver (VST) in LabVIEW: A Review
Abstract: AbstractOver the past few decades, the increasingly popular architecture of RF systems with software has become increasingly popular. Almost every commercial automated RF system (COTS) today uses application software for communication via the bus interface with the device. As the complexity of radio frequency applications is increasing, engineers are constantly faced with the dilemma of increasing functionality without increasing testing time and, ultimately, to verify the cost. Although improvements in …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 1–5 Read article
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Designing of Circular Patch Antenna Modified by Metamaterial Structure
Abstract: AbstractThis finding is an outcome of the research carried out on the patch with the introduction of metamaterial. A “Dual Split Hexagonal Ring” metamaterial structure is implemented in the ground plane to modify the parameters of patch antenna i.e., circular. This recommended antenna operates on 2.42 GHz. Circular patch alone was not efficient and cannot be applicable for any applications, therefore a dual ring split metamaterial structure was implemented to …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 3, 2018 · pp. 1–5 Read article
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Comparison & Improvement in Channel Estimation Techniques for Next Generation Network Using mm wave OFDM Channel
Abstract: This paper develops schemes for orthogonal matching pursuit (OMP), bayesian Cramer Rao Bound & ORACLE-LS channel estimation technique in milli-meter wave (mm- Wave) multiple-input-multiple-output (MIMO) systems that exploit the spatial sparsity inherent in channels. In simulation results shows comparison between ORACLE LS & orthogonal matching pursuit (OMP) on the basis of NMSE v/s SNR comparison between orthogonal matching pursuit OMP, MSBL, and TSBL-based & various channel estimation techniques for the …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 8, Issue 2, 2021 · pp. 1–6 Read article
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Secure Data Processing and Transmission Using Machine Learning Techniques
Abstract: The amount of data created by smart devices has drastically increased in recent years as a result of the quick technological improvements in those devices and their use in a variety of applications. As a result, the big data (BD) created by various devices may be too much for typical data analytics tools to handle. However, this exponential expansion of data provides numerous types of attackers with new chances to …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 9, Issue 3, 2022 · pp. 22–30 Read article
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Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node
Abstract: In this article an analysis of carbon nanotube field effect transistor based ring oscillator is performed. After analysis it was found that carbon nanotube transistor consumes less power in comparison to silicon transistor. CNFET is one possible candidate to substitute silicon-based integrated circuit (IC) technology, as the performance increase of conventional transistors witnessed during the last decades will arrive at its ultimate limits in the near future. Its present progress …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 51–54 Read article
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Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article
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Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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Comparative Analysis of High Speed Comparator for A to D Converters
Abstract: In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 4–10 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Memristor Modelling for Common Source Amplifier Using 180 nm Technology
Abstract: The objective of this research paper is on memristor modeling for common source amplifier circuit using cadence virtuoso tool at gpdk 180 nm technology. A memristor is the fourth element count after resistor, inductor and capacitor in fundamental electrical circuits assumption is proposed by Leon Chua, its characteristics is based on already occurred principles of voltages (V), current (I), flux (ᵩ) and charge (q). Ohm’s law states relation voltage to …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 45–54 Read article
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Design and Implementation of an Efficient Ternary Control Unit
Abstract: Multi-valued logic (MVL) is emerging as a thrust area of research due to several advantages offered by them over the conventional binary logic. Ternary logic is a promising alternative to the binary logic design technique thereby attracting a wide community of researchers to contribute in the design of ternary processor. The control unit is effectively the nerve center of a processor that plays a vital role in generating the appropriate …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 55–70 Read article
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Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System
Abstract: In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 38–43 Read article
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Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology
Abstract: This paper presents folding and interpolating ADC with resolution of 5 bit. The simulation result is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. This folding and interpolating ADC consumes less power than other, and it is 10 mW. The rate of conversion is 50 MS/S. So, it is suitable for low power application and medium resolution portable devices. Keywords: Folding ADC, interpolating, ADC, low …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 35–40 Read article
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Performance Analysis and study of losses in GaAs Multi Junction Solar cells using Current and Voltage Measurements
Abstract: Cross section coordinated, triple-intersection sunlight based cells with strain repaid quantum spots (QDs) in the GaAs center cell were developed by Metal-Organic Chemical Vapor Deposition (MOCVD). Structures with various quantities of QD layers are contrasted with gauge structures with no QDs. Quantum proficiency and light I-V estimations show an expansion in hamper thickness and debasement of the open circuit voltage for QD sun powered cells. The QDs don't work on …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 1, 2022 · pp. 1–7 Read article
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Floodplain Inundation Modeling and Mapping for Geray River: Nile Basin, Ethiopia
Abstract: Flood is among the most devastating natural hazards in the world claiming lives and properties more than any other natural phenomena. During high flow, the Geray River flooded the vicinity of the area and causes loss of cultivated land and life. The objective of this study describes the flood extent and depth in the Geray River for different flow conditions. This research involves the integration of HEC-HMS, HEC-RAS, and GIS …
Published in Journal of Water Resource Engineering and Management · Vol. 6, Issue 3, 2019 · pp. 25–45 Read article
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Rainfall-runoff Modeling using HEC-HMS Hydrologic Model for Guder River Watershed, Blue Nile Basin, Ethiopia
Abstract: Rainfall-runoff modeling is important for a number of hydrologic applications including flood forecasting, water resource planning and management. This study presents the result of a watershed rainfall-runoff modeling for Guder river watershed having area of 6597 km 2 using Hydrologic Engineering Center-Hydrologic Modeling Systems (HEC-HMS). The watershed runoff is varying spatially and temporally due to manmade factors and natural factors on the watershed. These issue needs efficient water resource planning …
Published in Journal of Water Resource Engineering and Management · Vol. 8, Issue 2, 2021 · pp. 62–77 Read article
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Appraisal of Household Potable Water Accessibility in Sub–Urban Areas of Oyo State: Geographic Information System and Remote Sensing Approach
Abstract: This study centred on assessing potable water accessibility in sub-urban areas using Fiditi as a case study. This study adopted a service area network and overlay operation in ArcGIS to achieve the aim of this study. Locational coordinates of all the facilities were obtained through Garmin 76 handheld GPS. Also, ground truthing was adopted to distinguish residential buildings from non - residential buildings. Coordinates (X.Y, Z) of the study were …
Published in Journal of Water Resource Engineering and Management · Vol. 10, Issue 1, 2023 · pp. 1–14 Read article
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Waste Plants as a Green inhibitor for Reinforced Concrete
Abstract: AbstractIn recent years, the use of inhibitors in producing high performance concrete has increased significantly as a result of chloride and sulfate attacks. The present inhibitors in market are toxic to the environment. Hence, the objective of the present investigation was to study a novel, eco-friendly and a hydrophobic green plant extracts’ inhibitor (rice husks) and study the effects of it on compression strength of reinforced concrete. The inhibitor above …
Published in Recent Trends in Civil Engineering & Technology · Vol. 7, Issue 3, 2017 · pp. 53–58 Read article