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85 articles for “Clock”
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FPGA Implementation of SoC Design using Softcore Processor and Custom Peripherals, Custom Instruction for Robotics and Automation
Abstract: The general definition of SoC is the on-chip integration of a variety of functional h/w blocks to suite a specific product application. In traditional technology designed using on board integration of functional blocks for any application, this leads to less performance. Nowadays productivity gap will be reduce by making compact, life of device and Time to market. So using FPGA demonstrating building of SoC using custom peripherals. FPGA (Field Programmable …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 1, Issue 3, 2013 · pp. 10–16 Read article
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Thermophilic Adaptation of Anaerobic Sludge for Electricity Production
Abstract: Normal 0 false false false EN-US X-NONE X-NONE Anaerobic digestion of biogas inside the digester occurs in a particular temperature range. Research shows that the production can be increased by 33% by switching over from mesophilic temperature range (3040 ° C) to thermophilic temperature range (5060 ° C). Even then, biogas plants generally work in mesophilic range because a large amount of energy is required to maintain the high digester …
Published in Journal of Alternate Energy Sources & Technologies · Vol. 2, Issue 2, 2011 · pp. 30–39 Read article
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VHDL Design of ARINC 429 Bus Protocol
Abstract: ARINC 429 is a data transfer standard for aircraft avionics which is also known as the Mark 33 DITS Specification (Digital Information Transfer System). It makes use of self-clocking and self-synchronizing techniques. ARINC-429 bus interface is used as a controlling function. It is a two-wire point-to-point serial data bus for control communications in Avionics. The bus operates at the speed of 100kb/sec; the ARINC429 is developed to provide interchangeability and …
Published in Journal of Aerospace Engineering & Technology · Vol. 6, Issue 2, 2016 · pp. 21–27 Read article
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A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology
Abstract: Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption as compared to the other CMOS design styles. This paper proposes a novel high speed flip flop design in 16 nm technology. The design was compared with the existing low power techniques in terms of power, and delay (clk-Q and D-Q). The proposed design was found to be 20% fast as compared to basic 9T …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 37–44 Read article
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Low Power, High Speed and High Density Magnetic Comparator using Spintronic Devices
Abstract: Energy efficient design is of paramount importance in the present era. Dynamic magnetic comparators are used to design high speed and low power ADCs (Analog to digital converters). This paper presents a novel conventional MTJ and motion of domains in a magnetic strip based magnetic double tail comparator, which is area and power proficient, compared to other comparators. The proposed magnetic double tail comparator consumes 15.225 µW power and 0.6369 …
Published in Nano Trends – A Journal of Nano Technology & Its Applications · Vol. 20, Issue 1, 2018 · pp. 27–34 Read article