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1218 articles for “Signals”
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Efficient Encoding And Decoding Block Turbo Codes
Abstract: A channel coding approach is performed to lower the noise and interference that erupted in the communication channel. There are indeed a myriad of alternative channel coding schemes that have been developed. Block and convolutional codes are the most prevalent. Turbo code is a new near-channel capacity error-correcting code that has been introduced recently. The information can be transmitted across the channel with a very low bit error rate using …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 9, Issue 1, 2022 · pp. 11–23 Read article
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Fault Detection Attainment for Embedded Cores based on Software Test Routines
Abstract: The test circuitry is designed in built-in-self-test (BIST) technique involves a system that applies the test signals and observes the corresponding system response. In this technique, the framework is embedded directly into the system hardware. The testing process performs efficiently, fastly and more economically than using an external test setup. Self-testing of embedded processors based on the test routines is an emerging method, since it employs a test resource partitioning …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 1–6 Read article
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AXI Bridge and DMA/Bridge Subsystem for PCIe
Abstract: We know that the present-day SOC design consists of many intellectual property cores with several communication protocols. To enhance the performance of the whole system, we need to improve the bridging and signal translation between these protocols. In this article, discussion has been carried out on PCIe and AXI protocol from AMBA. PCI Express, because of its various features like high speed, low power consumption, and good protocol efficiency can …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 23–29 Read article
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Design of Three-Stage Pipelined Floating Point Arithmetic Operators
Abstract: Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM and multiplexer …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 9–22 Read article
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A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault
Abstract: Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 72–78 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article
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Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology
Abstract: This paper proposes a review on study and analysis of an efficient fast low power 1 Kb SRAM cell using 90 and 45 nm Microwind technology. In this paper we have proposed the tentative improvement in performance parameters of SRAM cell like power dissipation, read or write speed, stability and signal to noise margin ration (SNM) using CMOS scaling.Keywords: SRAM, CMOS scaling, MicrowindCite this ArticlePathrikar A.K, Deshpande Rajkumar S. Design …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 1–3 Read article
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article
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Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System
Abstract: In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 38–43 Read article
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Design and RTL Implementation for AHB-APB Bridge on SoC
Abstract: The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 44–52 Read article
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A New TGC-Differential Input Stage to Modify Dynamic Comparator
Abstract: As the technology rapidly scaling down, the escalating demand for higher accuracy is putting a heavy pressure to find ways to get rid of one of the major issues among present day dynamic comparators i.e. random offset voltage generation. A number of offset calibration techniques have been presented to resolve this issue. It has become an important concern to analyze these techniques for scaled down technology nodes to cop up …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 74–85 Read article
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Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC
Abstract: As per emerging issues in analog-mixed signal (AMS) design towards high-speed and low power, limits the performance of high-speed applications. Circuit complexity, speed, offset voltage and resolutions are essential parameter of comparator that affects the analog-to-digital converter (ADC) performance. Based on specifications, to achieve lower offset voltage and higher load drivability of latched comparator is presented. Moreover, the circuit is able to reduce power dissipation as the topology is based …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 99–103 Read article
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Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy
Abstract: The development of digital circuits, digital signal processors and other data processing integrated circuits, comparators are challenged by large area consumption. Comparator is most basic and fundamental component that performs comparison operation. This paper proposes a new approach to design an area efficient two bit magnitude comparator. Comparison is done on the grounds of area and power consumed between circuit designed by novel strategy and preexisting CMOS technique. The novel …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 1–6 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA
Abstract: Complex multiplication is an important operation frequently used in the digital signal processing. This paper shows the resource utilization for a complex multiplication on Spartan3E by using a 9 bit floating point numbers. The proposed method clearly shows that resource utilization for complex multiplication is less than the IP cores proposed by the Xilinx Company. More over this paper shows how the significant and the exponent of the floating point …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 9–14 Read article
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Investigations on the impact of modulation formats and weather conditions in FSO link employing polarization division multiplexing and coherent detection-orthogonal frequency division multiplexing
Abstract: Free space optics (FSO) is a communication system where free space acts as medium between transceivers and they should be in line-of-sight for successful transmission of optical signal. Medium can be air, outer space, or vacuum. This system can be used for communication purpose in hours and in lesser economy. There are many advantages of FSO like high bandwidth and no spectrum license. The transmission in FSO is dependent on …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 2, 2020 · pp. 17–25 Read article
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Adaptive Hysteresis Band Current Controller for the Shunt Active Power Filter Using the d-q0 Reference Frame Theory
Abstract: Recent wide spread applications of power electronic equipment has caused an increase of the harmonic disturbances in the power systems. The nonlinear loads draw harmonic and reactive power components of current from AC mains. Here an adaptive hysteresis band current controlled shunt active power filter is presented to eliminate harmonics and to compensate the reactive power of three-phase rectifier. This current controller changes the hysteresis bandwidth according to modulation frequency, …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 2, 2020 · pp. 1–7 Read article
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Hardware Implementation of Discrete /Inverse Discrete Cosine Transform Using Redundant Number System CORDIC Processors
Abstract: Rapid enhancement in multimedia service running on portable application has forced the development of high quality and low power implementation of complex signal processing algorithms. Image and video processing are typical application of multimedia system. Image compression and decompression using DCT/IDCT are the two algorithms commonly used in MPEG standard of image processing. For an image of N x N size, DCT/IDCT would require N4 multiplications and increases complexity. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 1, 2021 · pp. 35–42 Read article