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781 articles for “voltage (V)”
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A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic
Abstract: Domino circuits are widely used these days in the design of modern-day microprocessors because of their high speed and less area overhead compared to static logic style. In this paper, a new domino-based 4:1 multiplexer circuit has been designed which finds extensive use in register files and execution units where large amounts of data have to be broken into smaller chunks so that the processor can manipulate it more easily …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit
Abstract: A size and power efficient current-mode decimal adder is proposed in this paper. The proposed adder does not use binary coded decimal (BCD) number system for processing the decimal data like other decimal adders. Instead, it processes the decimal data as the actual decimal inputs. The proposed adder can be used as a decimal half adder as well as a decimal full adder. The adder is based on simple decimal …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 18–23 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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Design of High-Speed TIQ Comparator for Flash-Type ADC for (WPMOS/LPMOS) > 1
Abstract: Comparator is the circuit that compares an analog signal with the reference signal and produces the binary output based on comparison. A Comparator is the main block in the ADC design as it directly affects the conversion rate of an ADC. Depending on the type and architecture of the comparator, the comparator can have significant impact on the performance of the target application. The speed and resolution of an ADC …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 47–52 Read article
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A Low Power Variable Gain Amplifier for Biomedical Application
Abstract: This paper describes the design and simulation of low power variable gain amplifier used for biomedical application like hearing aid, Electronic Cardiograph and neural recording system. The MOS transistor is designed to operate in subthreshold region for low power application. The gain of amplifier is changed by selecting different values of input capacitor in the frequency range of 20 Hz–20 KHz. The simulated total power dissipation is 3µW. The gain …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 7–12 Read article
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Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect
Abstract: This paper addresses one of the aspects of the high frequency effects, namely the skin effect. The basicproblem with skin effect is that it attenuates the high frequency components of a signal more than that ofthe low frequency components. Due to the increase in operating frequency and die sizes, RC models arebecoming insufficient for analysis of global VLSI interconnects. Accurate noise modelling for RLC lines isthus critical for timing and …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 31–44 Read article
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Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System
Abstract: In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 38–43 Read article
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An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based Amplifier for Analog Signal-based Applications
Abstract: A low-noise amplifier (LNA), which is based on the cascode feedback methodology, has been commonly used for various wireless protocol-based network applications nowadays. It is so because this topology ensures that the low-noise amplifier (LNA) can achieve quite a high performance and thus, provides a high qualitative output. This amplifier is operated with a low voltage supply in the range of few volts that requires that the impedances of the …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 7–15 Read article
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A Differentiator Based on Second Generation Current Controlled Conveyor
Abstract: A new second generation current controlled conveyor (CCCII) with programmable gain at output terminal ‘Z’ is presented in this paper. The inherent advantages of the proposed circuits are low supply voltage requirement of ±0.85 V, small input parasitic resistance in the range of 29.12 Ω–297.71 Ω for a current range of 10 µA–300 µA, low power dissipation of 79.39 µw and low DC current error of 0.068%. The proposed CCCII …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 89–95 Read article
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Design and Implementation of Low Power 8-bit Level Crossing ADC
Abstract: Implantable medical devices, electronic gadgets, wireless communication elements and many other such applications require low power electronic circuits. Analog to digital converters are essential part of most of such circuits. This paper presents a design of the level crossing analog to digital converter (LC-ADC) architecture. The proposed circuit and layout has been implemented in semi-conductor laboratory (SCL) 180 nm technology and its performance was evaluated using cadence virtuoso at supply …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 33–43 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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Design of High-Speed and Low-Power Carry Skip Adder
Abstract: In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 35–44 Read article
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Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops
Abstract: This paper presents phase frequency detector using different gates like AND, NOR and NAND and comparative simulation result analysis is carried out. The simulation is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. NAND based PFD has lowest power consumption then other and it is 4.2587 µW at 1 GHz Frequency and dead zone to 18 ps which means having approximately zero dead zone problem. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 18–28 Read article
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Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture
Abstract: Content Addressable Memory (CAM) is a storage unit used for faster accessing of lookup table that reduces processing time for search operation. It is mainly used very-high-speed searching applications like computer networking devices. The MAC address table is implemented with a CAM so that the destination port can be easily detected by reducing the switch’s latency. CAM gets its high speed of operation by parallel search mechanism. This paper proposes …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 29–34 Read article
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Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology
Abstract: This paper presents folding and interpolating ADC with resolution of 5 bit. The simulation result is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. This folding and interpolating ADC consumes less power than other, and it is 10 mW. The rate of conversion is 50 MS/S. So, it is suitable for low power application and medium resolution portable devices. Keywords: Folding ADC, interpolating, ADC, low …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 35–40 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 28–34 Read article
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Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability
Abstract: The demand of static random access memory cell in embedded memories is rapidly increasing. To design SRAM is continuously becoming difficult due to limitation of weaker write margin, degraded data stability and higher leakage power consumption. In order to overcome these limitations, new 8T SRAM has been explored. The simulation results depicts better data stability, low access delay and decreased leakage power consumption. Alternatively, proposed cell with sleep transistor and …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 35–44 Read article
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Exploring the Potential of Adiabatic Logic for Low Power Nano-scale VLSI Designs
Abstract: Low power dissipation has emerged as one of the main research areas due to the ongoing scaling down of device technology in the area of VLSI circuit design. Adiabatic logic gates are a practical answer to the rising demand for low power portable gadgets. Various adiabatic logic families, including 2N-2N2P, PFAL (Positive Feedback Adiabatic Logic), DCPAL (Differential Cascode and Pre-resolved Adiabatic Logic), and a suggested circuit centred on the PFAL …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 6–14 Read article
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The Comprehensive Study of Gallium Nitride (GaN) Semiconductor Technology
Abstract: Silicon is an important material in the field of semiconductors because of its special qualities. It has good semiconductor properties, is affordable, and can be found easily. However, it is becoming clear that silicon-based devices are reaching their limits in terms of what they can do. As a result, the search of alternative materials has been initiated. Gallium Nitride (GaN) is one such material. GaN is a type of semiconductor …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 1–11 Read article