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24 articles for “Hardware Descriptive Language”
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article
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THD Minimization of 27 Level Inverter using FPGA Control Strategy
Abstract: Normally single phase inverter gives only +230 V or –230 V. But multilevel inverter gives the variable output voltage in various levels and also the harmonics are reduced. If harmonics are produced, it affects the output of the load. Most of the industrial applications rely on Induction motors because of the reliable operation, low cost and simple construction. So the Multilevel inverter output is connected to the Induction motor. Here …
Published in Journal of Power Electronics and Power Systems · Vol. 3, Issue 3, 2013 · pp. 39–46 Read article
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FPGA Implementation of LDPC Codes
Abstract: AbstractLow Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 21–28 Read article
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Design and Implementation of an Efficient Ternary Control Unit
Abstract: Multi-valued logic (MVL) is emerging as a thrust area of research due to several advantages offered by them over the conventional binary logic. Ternary logic is a promising alternative to the binary logic design technique thereby attracting a wide community of researchers to contribute in the design of ternary processor. The control unit is effectively the nerve center of a processor that plays a vital role in generating the appropriate …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 55–70 Read article