All articles
36 articles
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An Overview on VLSI based Hardware Security in IoT Node
Abstract: In the coming era, security will not be a feature we add to an IoT device; it will be a property inherent to its transistor-level design. By encoding security into the VLSI architecture, we move away from the fragile "software-only" paradigm and toward a future where the identity of the device is as immutable as the laws of physics. The rapid proliferation of Internet of Things (IoT) devices has transformed …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design
Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems
Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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How small circuits power big technology in the world of VSIL
Abstract: Very Small Integration Level (VSIL) circuit technology represents an emerging class of ultra- compact, low-power electronic design methodologies that enable the creation of highly efficient and scalable systems. This article explores the fundamental principles behind VSIL circuits, including device miniaturization, optimized layout strategies, adaptive power management, and noise-resilient architectures. We also look into the methodical engineering of VSIL circuits to satisfy the ever-tougher performance, robustness, and long- term energy-efficiency demands …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 44–53 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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Navigating the Antenna Frontier for Emerging IoT Technologies
Abstract: Internet of Things (IoT) is rapidly transitioning from niche applications to a pervasive, interconnected fabric of intelligent devices, demanding unprecedented levels of performance, reliability, and miniaturization from its constituent components. At the heart of this revolution lies the antenna, the crucial interface between the digital and physical realms. This paper delves into the intricate and evolving landscape of IoT antenna design, specifically addressing the unique challenges and opportunities presented by …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 1–10 Read article
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DFT Compatible Low Power EDAC Based on Clock Gating
Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article
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Securing IoT Wilderness with VHDL
Abstract: The Internet of Things (IoT) has revolutionized connectivity by integrating billions of devices and reshaping industries. However, this vast network also brings substantial security concerns. From compromised sensors to hijacked industrial control systems, the vulnerabilities within IoT devices can have far-reaching consequences. Hardware Security Modules (HSMs) provide a reliable and secure environment for performing cryptographic operations and safeguarding sensitive data. This article explores the crucial role of VHDL (VHSIC Hardware …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 29–40 Read article
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VHDL Programming for Secure Bootloaders in IoT Security
Abstract: The proliferation of Internet of Things (IoT) devices has brought unparalleled connectivity and convenience. However, this increased connectivity comes with a heightened risk of security vulnerabilities. One of the most critical areas for securing IoT devices is the bootloader, the software responsible for initializing the device and loading the operating system. A compromised bootloader can lead to a complete takeover of the device, making it a prime target for malicious …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 19–28 Read article
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VLSI – Power, Expansion and Versatility
Abstract: The evolution of Very Large-Scale Integration (VLSI) technology has significantly transformed the landscape of modern electronics, driving innovations across diverse industries. This article explores the key attributes of VLSI, focusing on its power, expansion, and versatility. VLSI's power lies in its ability to integrate thousands to millions of transistors on a single chip, enabling the development of high-performance, energy-efficient devices. The expansion of VLSI technology is exemplified by its application …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 1–8 Read article
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Reconfigurable AES Based AEAD For Multi-Mode Operation with Lightweight Compatibility
Abstract: The proposal is for a lightweight, multi-mode, reconfigurable authenticated encryption system with associated data (AEADs) based on AES. It is challenging to effectively integrate different AEADs in hardware because each one has its own mode of operation and/or subfunctions, even though some major AEADs share several basic components (such as the XOR-Encryption-XOR (XEX) scheme, block chaining, and advanced encryption standard (AES). This paper proposes hardware that effectively combines the basic …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 54–68 Read article
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Modelling Electronic Diode Networks with PSPICE Simulation
Abstract: The dual of Thevenin, Norton equivalent circuit is used in place of any circuit/network of linear sources and immittances at at a given frequency. Both Thevenin with Norton theorem is useful for analyses and modification of circuits, to study /obtain network’s steady state response and initial condition. Methods to represent different circuits with Thevenin/Norton impedances connected at desired nodes are given using Spice/Pspice. The Thevenin/Norton impedances connected are of other …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 2, 2024 · pp. 17–37 Read article
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Transforming IoT Connectivity Through VLSI Technology
Abstract: Device communication has been completely transformed by the emergence of the Internet of Things (IoT), and very large-scale integration (VLSI) has been essential to this change. The development of small, energy-efficient devices that are essential to IoT applications is made possible by VLSI technology, which allows thousands to millions of transistors to be integrated on a single chip. By enabling higher processing capabilities and seamless connectivity, VLSI not only enhances …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 2, 2024 · pp. 1–11 Read article
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Piezoelectric Energy Harvesting Using A 10x10 Sensor Matrix with Integrated Circuit Design for Pressure Control
Abstract: This project aims to create a system that generates energy using piezoelectric technology, designed as a rectangular tile platform. The platform has two layers of sensors arranged in a 10 × 10 grid, connected in a mix of series and parallel setups. The top layer acts as a surface for external forces, like footsteps, while springs connect the layers to control pressure and maximize energy generation. A rectifier ensures the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 2, 2024 · pp. 47–53 Read article
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Advancing UAV Video Transmission: A Full-Duplex System with RF and Signal Processing for Reliable, Long-Range HD Communication
Abstract: Unmanned aerial vehicles (UAVs) have transformed industries by enabling advanced aerial imaging and data collection. However, transmitting high-definition (HD) video from UAVs to ground stations poses challenges such as limited range, bandwidth constraints, and interference. This paper presents the development of an HD, full-duplex video transmission system using cutting-edge electronic technologies, including advanced radio frequency (RF) systems and signal processing. These electronic systems are designed to ensure fast, reliable, and …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 2, 2024 · pp. 38–45 Read article
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Biometric Fingerprint Systems for Secure and Efficient Attendance Tracking in Workplaces and Universities
Abstract: A fingerprint attendance system, which uses each person's unique fingerprint rather than more conventional techniques like sign-in sheets or ID cards, is a simple and dependable approach to keeping track of who is present. The device instantly compares the user's finger to the fingerprint on file when they place it on a scanner, thereby recording their attendance. This avoids errors such as someone signing in on behalf of others or …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 2, 2024 · pp. 12–17 Read article