Design and Validation of Low Power High Speed area effective comparator using CMOS Technology

Maharaja Sangeetha; Gangula Swathi

doi:10.37591/rtecs.v10i2.7766

Abstract

The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds having effective area and power dissipation which can also reduce the proposedcomparator design's space and power consumption. The proposed model is carried out bitwise starting with the least significant bit and working way up to the most significant bit. This process continues only if the bits are equivalent, and the result is what is known as a Parallel prefix tree structure. Two distinct modules make up the proposed comparator structure methodology which are Final unit (FU) and comparison evaluation unit (CEU) are the first and second units, respectively. Validated findings from the methodical organization of repeating logic cells are used to create tree structures. The FU module authenticates the result by relying on CEU results. The proposed architecture's use of structured VLSI technique enables area derivation using analytical method relating transistor count and total delay, which can be understood in terms of operand bit width. While running the virtuoso simulations at 1 GHz with both old model and 45GPDK CMOS technology, it has been found that the design has been enhanced the operating speed by 31.92% while reducing power usage by 77.76%.

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