Transistor Full Adder: A Comparative Performance Analysis

SIMI P THOMAS; Aparna Jose

doi:10.37591/rtecs.v5i3.1364

Abstract

AbstractIn this work the static energy recovery full adder named 10T13A with reduced 10 transistors is implemented. The fan in and fan-out of gates is also reduced by reducing number of transistors. Calculation of 10T13A full adder various parameters has been at 45 nm technology and compared with MTCMOS technique based 10T13A Full Adder. The active power has been calculated at 45 nm technology using Cadence Virtuoso Tool. Simulation results show that power consumption of the circuit is reduced and delay has also been reduced at 45 nm technology. The low value of power delay product (PDP) also known as figure of merit is desired and the value of power delay product of proposed 10T13A Full Adder with MTCMOS technique is reduced to a large extent. The comparison showed that the implementation of the 10T full adder using MTCMOS technique would be better at 45nm technology as compared to 10T full adder. The results confirmed that MTCMOS technique reduces the power and leakage current significantly and makes the circuit suitable for practical applications.Keywords: 10T13A full adder, MTCMOS technique, power delay productCite this ArticleSimi P Thomas, Aparna Jose. Transistor Full Adder: A Comparative Performance Analysis. Recent Trends in Electronics & Communication Systems. 2018; 5(3): 22–31p.