Electrical Performance of the Silicon Nanowire Double Gate FET

Dayal C. Sati; Manoj Kumar; Vivek Kumar; Nripender .

Abstract

Silicon nanowire (SiNW) metal-oxide-semiconductor field-effect transistor (MOSFET) is a promising candidate of future CMOS device for further scaling. As the cross-sectional dimensions of SiNW channel is very small, cross-sectional shapes should affect electrical characteristics of SiNW FETs. In this work, effects of cross-sectional shapes of gate stack formation on (i) properties of double gate of SiNW FET; (ii) carrier transport properties including on-current, effective carrier mobility and inversion charge density; (iii) electrostatic controllability are investigated. A novel device structure, semi gate-around structure is proposed in this work, which is similar to double-gate structure. Silicon nitride sidewalls are filled at the pedestal of the double-gate structure, which reduces steepness of three-dimensional structure. Therefore, over-etching step time during gate patterning process is reduced. To establish design guideline of cross-sectional shapes of SiNW FET to achieve high on-current (ION), SiNW FETs with various cross-sectional shapes are designed and characterized. Among rectangular, half-circular, tear-like, and tall rectangular cross-sections, SiNW FET with rectangular cross-section exhibits highest on-current for nFET at the channel height of 12 nm and width of 19nm. For analysis of transport properties, effective carrier mobility (eff) and inversion charge density (Qinv) are evaluated. Qinv of rectangular cross-section is increased because of high-density inversion carrier regions around corners compared with planar SOI nFET.

Abstract

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