Leveraging cross-coupled domino logic for low-power, two-port SRAM with resilience to Differential Power Analysis (DPA) attacks

Mohil Sandip Desai; Dr. Anu Gupta

Abstract

Side channel attacks have become a serious threat to embedded and cryptographic systems. These attacks can be deployed by capturing the power consumption traces or electromagnetic radiations from the power and communication channels. SRAM is vulnerable to such attacks. Power consumed by SRAM for various read and write operations can express the information about bits being read from or written into the bit-cells which eventually exposes the instructions and data being processed by the processor. This paper reports a topology for two-port SRAM bit-cell that consumes equal power for each read and write operation. Since bit-cells are already differential, we can leverage DPA resiliency by incorporating dynamic nature into them. Proposed 11-T SRAM bit-cell uses cross-coupled domino logic. This topology ensures low-power consumption, less delay overhead along with resilience to DPA attacks as demanded by embedded applications. Performance metrics, DPA resiliency metric and stability metrics have been comprehensively compared for the proposed circuit and the circuits previously proposed in the literature.

Abstract

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