Journal of Microelectronics and Solid State Devices
Volume 5, Issue 1 (2018)
Published
Table of contents
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Computer Modeling of Organic Thin Film Transistors (OTFTs) using Verilog-A
Abstract: AbstractOrganic electronics has drawn considerable attention of the researchers with organic thin film transistors (OTFTs) as key components for various applications. Compared to the silicon industry where public models are well defined and commonly used to provide designers with a relative good description of any process, organic devices are still lacking for their complete device models that can fully describe their electrical characteristics. Therefore, compact model development for OTFTs is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 1–7 Read article
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Analysis of Signal Delay in Carbon Nano Tube based Interconnects at 32 nm Technology Node
Abstract: AbstractIn the present world demand for portable devices and high speed processor is rising which brings out a challenging issue of scaling for designers. In this paper, we have presented the effect of copper and CNT based interconnects for different length at 32 nm technology node. The performance of both types of interconnects are analyzed and compared in form of propagation delay. Propagation delay in interconnects between the elements is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 20–26 Read article
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Numerical Simulation and Modeling of Graphene Field Effect Transistors for High Frequency Applications
Abstract: AbstractIn this paper numerical simulation of graphene field effect transistor (GFET) has been performed using finite element method by solving Poisson's equation, continuity equation and energy balance equation self consistently. Various performance characteristics including charge distribution, band gap energy, transfer and output characteristics, electrostatic potential distribution and transconductance have been extracted.Keywords: Graphene field effect transistor (GFET), energy balance equation, mobility, ambipolar, numerical simulationCite this ArticleAshish Jha, Dwivedi ADD. Numerical Simulation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 27–33 Read article
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Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits
Abstract: AbstractCarbon nanotube Field Effect Transistors (CNTFET) offer various benefits as compared to other FETs. Many circuits can be constructed using PCNTFETs (P-type CNTFET) and NCNTFETs (N-type CNTFET) similar to the PMOS and NMOS of the CMOS technology. The CNTFETs employ carbon nanotubes in the channel of the device to provide a path for the ballistic conduction of electrons. The different ratios of number of tubes in channel of the PCNTFET …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 34–40 Read article
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Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology
Abstract: AbstractThis paper presents the design and analysis of double gate FinFET complimentary pass transistor logic (CPL) multiplexer. The circuit of multiplexer (MUX) using CPL is used for comparison of performance parameters like average power consumption, rise/fall time, delay, slew rate, PDP and EDP. Multiplexer is a digital circuit, it has inputs and select line; select lines are used for select input lines to transfer data to the output end. The …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 41–48 Read article
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Distribution Power Loss Minimization by Network Reconfiguration and DG Placement
Abstract: AbstractThe paper presents an efficient algorithm for network reconfiguration associated with DG allocation to minimize real power losses in radial distribution networks. Selective Particle Swarm Optimization algorithm (SPSO) is used to find new tie switches. Allocation of DG units has been done by new analytical approach. The proposed analytical method for optimal DG placement is developed based on a new mathematical formulation. DG type-I is used to solve the problem. …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 8–19 Read article