Design And Validation of High Efficiency Of 10T Sram with High Recoverability Of Multi Node Soft Error

Punem Sangeetha; Vijaykumar R Urukude

doi:10.37591/josdc.v10i2.7566

Abstract

Sensitive nodes' critical charge is decreasing, which increases the soft-error vulnerability of SRAM cells used in aerospace applications. A single event upset (SEU) occurs when a radiation particle hits a sensitive node in a typical 6T SRAM cell, flipping the data that has been stored in the cell. Consequently, a Soft-Error-Aware Read-Stability-Enhanced Low Power 10T (SARP10T) SRAM cell is suggested in this project to reduce SEUs. The quadro cell exhibits greater promise as it provides strong performance with a moderate area overhead. Nevertheless, our analysis reveals that Quatro encounters a high rate of write failures with scaled technology parametric fluctuations, which hinders the use of this SRAM cell. Nevertheless, our analysis reveals that Quatro encounters a high rate of write failures with scaled technology parametric fluctuations, which hinders the use of this SRAM cell. SARP10T is compared with QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T—other newly announced soft-error-aware SRAM cells—to assess its relative performance. If a radiation attack flips the node values, all SARP 10T's sensitive nodes can recover their data. Moreover, single event multi-node upsets (SEMNUs) caused at its storage node pair can be recovered from using SARP10T. In addition to these benefits, the suggested cell has the best-read stability since it can recover from any disruption thanks to the '0'-storing storage node, which the bit line can access directly during read operations. Moreover, SARP10T uses the least amount of hold power. In comparison to most of the comparison cells, SARP10T also shows better write capabilities and a shorter write delay. The suggested cell achieves all these benefits with only a slightly longer read delay and a slightly higher read and write energy consumption.

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