Reduce Timing in Physical Design

S. Mohan Das; Ashath Balanna

doi:10.37591/jomsd.v6i3.3690

Abstract

AbstractThe physical design flow consists of producing a production worthily from a gate level net list subject set of constraints. Here, focuses on the reduce the timing from floor plan to routing stage. Because performance of a chip depend on the timing. Mainly in routing stage manually adding the buffers and upsizing the drive strength in violating the time paths. It also surveys some physical design flows. The outlines a refinement based flow. Buffers are inserted in the design to drive a load that is too large for a logic cell to efficiently drive. If the net is too long then the net is broken and buffers are inserted to improve the transition. The data path will be optimized the net delays it increases the driving capability.Keywords: Upsizing, refinement, data path, bufferingCite this ArticleS. Mohan Das, Ashath Balanna. Reduce Timing in Physical Design. Journal of Microelectronics and Solid-State Devices. 2019; 6(3): 28–36p.