2 publications

• Published Subscription 1 Feb 2020

  Reduce Timing in Physical Design

  By S. Mohan Das, Ashath Balanna

  Abstract: AbstractThe physical design flow consists of producing a production worthily from a gate level net list subject set of constraints. Here, focuses on the reduce the timing from floor plan to routing stage. Because performance of a chip depend on the timing. Mainly in routing stage manually adding the buffers and upsizing the drive strength in violating the time paths. It also surveys some physical design flows. The outlines a …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 3, 2019 · pp. 28–36 Read article →

• Published Subscription 1 Feb 2020

  Reducing Cell Density Congestion Issue in Chip Design

  By S. Mohan Das, Shaik Mahammad Rafi

  Abstract: AbstractThe congestion issues reduce with the help of shrinking process technologies. Here, typical placement objectives involve reducing cell density congestion in a chip design. Congestion reducing is the least understand; however, it models route ability most accurately. The congestion issue is cell density (commonly believed to be very effective) does not always work well, so here by applying the partial block technique for the cell density is among the best …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 3, 2019 · pp. 11–17 Read article →