Literature Survey of On-chip Architectures and Arbitration Algorithms

Tejas U. Patel; Devendra Patle

doi:10.37591/jomea.v4i1.5247

Abstract

Today micro-electronic products are influencing the ways of communication, learning and entertainment. The key driving force for the developments during decades is the System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips. Not only functionally enriched, these products such as mobile phones, notebooks and personal handheld sets are becoming faster, smaller-in-size, larger-in-capacity, lighter-in-weight, lower-in-power-consumption and cheaper. In this survey, communication architectures of SoC are discussed whose design is very important in overall performance of chips. These architectures fulfil the performance needs of multimedia applications, telecommunication architectures, network security and other application domains and limiting the power consumption through the use of specialised processing elements and architecture alongside. In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. In this paper, different architectures are compared and the hardware challenges involved in designing MPSOCs are discussed.

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