STM Journals Peer-reviewed research from Consortium e-Learning Network

2 publications

  • Published Subscription

    Literature Survey of On-chip Architectures and Arbitration Algorithms

    By Tejas U. Patel, Devendra Patle

    Abstract: Today micro-electronic products are influencing the ways of communication, learning and entertainment. The key driving force for the developments during decades is the System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips. Not only functionally enriched, these products such as mobile phones, notebooks and personal handheld sets are becoming faster, smaller-in-size, larger-in-capacity, lighter-in-weight, lower-in-power-consumption and cheaper. In this survey, communication architectures of SoC are discussed whose design …

    Published in Journal of Microcontroller Engineering and Applications · Vol. 4, Issue 1, 2017 · pp. 17–23 Read article

  • Published Subscription

    Implementation of Weighted Round Robin Algorithm in Shared Bus Architectures

    By Tejas U. Patel, Devendra Patle

    Abstract: AbstractThe application domain of System-On-Chips (SoC) includes mobile devices, end terminals, multimedia terminals, automotive, set-top-boxes, games, processors etc. The SoC design paradigm relies heavily on reuse of intellectual property cores, enabling designers to focus on functionality and performance of the overall system. This is possible if IP cores are equipped with highly optimized interface for plug and play insertion into communication architecture. To this purpose the virtual Socket Interface Alliance …

    Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 34–40 Read article

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