STM Journals Peer-reviewed research from Consortium e-Learning Network

Current Trends in Signal Processing

FPGA Implementation of Reed Solomon Encoder and Decoder

  1. Saurabh Singh
  2. Mohan Khambalkar
  3. Ankur Varma

Abstract

Abstract: Forward Error Correcting (FEC) is a technique employed to enhance data security & reliability. An efficient coding technique is essential to ensure data security. Reed Solomon Codes are widely used to provide error correction capability against burst error. This paper presents the design & FPGA implementation of RS (7, 3) codes. The design is entirely parameterized and can be scaled readily for a wide range of a number of message symbols. Keywords: FEC, Galois field, Reed Solomon codes, RS encoder, RS decoderCite this ArticleSaurabh Singh, Mohan Khambalkar, Ankur Varma. FPGA Implementation of Reed Solomon Encoder and Decoder. Current Trends in Signal Processing. 2019; 9(1): 10–16p.
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