STM Journals Peer-reviewed research from Consortium e-Learning Network

2 publications

  • Published Subscription Review Article

    Implementation of a 4-Bit Synchronous Counter in SkyWater 130 nm CMOS Technology Using Open-Source EDA Tools

    By Maitra Shah, Mitesh Limachia, Narendra Chauhan, Sagar Kavaiya, Purvang Dalal

    Abstract: As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed …

    Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 2, 2026 Read article

  • Published Subscription Review Article

    Architectural Evolution of RISC Processors: From Early Research Prototypes to Modern Industrial Implementations

    By Aditya Chauhan, Mitesh Limachia, Narendra Chauhan, Purvang Dalal

    Abstract: This paper surveys the architectural evolution of Reduced Instruction Set Computer (RISC) architectures from early research prototypes to modern industrial processors, tracing four decades of design refinement across academic, embedded, server, mobile, and open- hardware ecosystems. Core ISA principles, pipeline evolution, compiler–hardware co-design, and quantitative performance modeling are analyzed through four representative industrial implementations: MIPS 74K, SPARC T4, ARM Cortex-A72, and SiFive U74 (RISC-V). Each processor is examined in terms …

    Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 29–39 Read article

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