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Published Subscription Original Research
Study the Effect of Applied Gate Voltage on Threshold Potential and Carrier Transport Behavior of Three-Terminal Novel Prototype Device having Configuration P-type Si/SiO2/CuFeS2/AlBy Asmita Patra, Suman Mahata, Animesh Layek
Abstract: This study presents a trial approach for the fabrication and characterization of a novel p-Si/SiO₂/CuFeS₂/Al field-dependent three-terminal electronic device designed to investigate charge transport behavior across multiple semiconductor junctions under externally applied bias voltages. The proposed prototype incorporates CuFeS₂ (chalcopyrite) as the active semiconductor layer, marking its first reported application in a field-induced electronic device architecture. The device was fabricated using a layered heterostructure consisting of p-type silicon, a silicon …
Published in International Journal of Crystalline Materials · Vol. 3, Issue 2, 2026 · pp. 1–7 Read article →