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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM CellBy Jitendra Krishna Arya, Ashish Raman
Abstract: VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 73–77 Read article →