1 publication

• Published Subscription 30 Dec 2017

  Design of 10T SRAM Cell for Low Power and High Speed Applications

  By Rajat Gupta, Amit S. Rajput, Nikhil Saxena

  Abstract: AbstractThis paper presents techniques for designing a low-power and higher read speed Static Random Access Memory (SRAM) cell. The cell achieves low power dissipation due to Virtual Ground (VGND) scheme and provides higher read performance due to Forward Body Biasing (FBB). Design metrics of the proposed SRAM cell was studied and compared with that of CON 6T, CON D10T, TG 8T, 9T, and ST-10T SRAM cells. It was observed that …

  Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 16–27 Read article →