VLSI design
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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A well-planned strategy for a career path in VLSI design
Abstract: Very Large Scale Integration (VLSI) design is still one of the most active and important areas of the semiconductor industry. It is behind new developments in AI, 5G, automotive electronics, and high-performance computing. As companies like Intel, TSMC, and NVIDIA work to improve advanced-node technology, the need for qualified VLSI engineers is growing. However, people who want to work in this industry typically don't know what technical skills, tools, and …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 28–39 Read article
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Optimizing Routing and Placement of VLSI Circuits with Differential Algorithms and Neural Networks
Abstract: The performance of modern VLSI systems is heavily influenced by power constraints, necessitating precise power estimation and effective optimization techniques. Traditional methods, such as gate-level simulations, are often slow and computationally intensive. This paper introduces DRPENN (Differential Algorithm for Routing and Placement Optimization using Neural Networks), an innovative solution that combines a Switching Activity Estimator (SAE) with a neural network-assisted differential algorithm. By leveraging toggle rates from simulations to train …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 14–20 Read article