UVM Register Layer

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• Published Subscription 5 Nov 2015

  Implementation of Register Access Methods for Device Configuration Using UVM

  By Jyoti Dahiya, Neeraj K. Shukla

  Abstract: Verification of hardware registers conjointly with their monitoring forms a huge part of any verification project. Verification using universal verification methodology (UVM) register layer enables reusability, which consequently eliminates the dependency of register layer on protocol thereby saving time by evading efforts of rewriting register sequences once the protocol changes. This paper constructs the advanced high performance bus (AHB) register verification environment to ease design configuration, thereby promoting reusability and …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 132–138 Read article →