Parallel Processing
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MAC Unit Implementation on FPGA
Abstract: Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 29–37 Read article
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Role of Beowulf Clusters in Next-Generation Military Applications: A Comprehensive Study
Abstract: Beowulf clusters, which utilize cost-effective commodity hardware combined with open-source software for parallel computing, have emerged as a viable and efficient solution for high-performance computing needs. This paper explores their growing relevance and practical applications in modern and future military technologies. Contemporary military operations increasingly rely on rapid data processing, real-time intelligence, high-fidelity simulations, and autonomous decision-making systems. Beowulf clusters offer scalable and adaptable computational power that supports these demands …
Published in Journal of Advances in Shell Programming · Vol. 12, Issue 2, 2025 · pp. 01–07 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article