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• Published Subscription 10 Apr 2019

  Impact of Spacer Engineering on SOI Junctionless FET Performance Using TCAD Simulation

  By P. Sasikala, Priscilla Scarlet, K. K. Nagarajan, R. Srinivasan

  Abstract: In this paper, the impact of spacer engineering on 10 nm gate length planar SOI (Silicon On Insulator) junctionless transistor performance is studied using Sentaurus TCAD simulator. Spacer length and spacer permittivity of the device are taken as two controllable parameters. DC performance metrics, ION, IOFF, ION/IOFF ratio, unity gain frequency (fT) and non quasi static delay (NQS) are investigated for various spacer lengths and spacer permittivity. The simulation results …

  Published in Journal of Materials & Metallurgical Engineering · Vol. 6, Issue 2, 2016 · pp. 42–52 Read article →