Clock tree synthesis (CTS)

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• Published Subscription Original Research 13 Dec 2025

  RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor

  By Abhishek Patel, Pankaj Verma

  Abstract: This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages …

  Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 1–10 Read article →