Cadence
2 articles · search the full text for this term
-
Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic
Abstract: This study utilizes the recent development of CMOS transistors to construct an energy-efficient Full adder-based CMOS 4-2 compressor. The CMOS Exclusive-OR-Exclusive-NOR component and multiplexer used in the transmission logic of the novel CMOS compressor include eight transistors. The XOR-XNOR logic style is the most efficient and effective due to its speed and reduced power consumption. Utilizing an operational supply voltage of 0.7 V and 90nm CMOS technology, the Cadence Virtuoso …
Published in Recent Trends in Electronics Communication Systems · Vol. 12, Issue 3, 2025 · pp. 1–8 Read article
-
RTL to GDSII Implementation UART using Verilog and Cadence tools
Abstract: The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 1–7 Read article