Boolean function

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• Published Subscription 19 Jul 2019

  Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation

  By Usha Sandeep Mehta, Vaishali Dhare, Harikrishna Parmar, Rahul A. Shah

  Abstract: The reduction in hardware requirement for any application does not only guarantee the reduction of chip area but also significantly reduces the corresponding power consumption and delays. Hence, any heuristic used to reduce the hardware requirement for given logic is always well justified. In this paper, the number of pass gates required to implement the given Boolean Logic is reduced by sizeable amount with use of the proposed algorithm for …

  Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 24–34 Read article →