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190 articles for “VLS”
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Comparative Analysis of High Speed Comparator for A to D Converters
Abstract: In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 4–10 Read article
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4-Bit Magnitude Comparator Design using Different Logic Styles
Abstract: 4-Bit Magnitude Comparator using various logic styles is explained here. Comparison is one of the common arithmetic operations that is used to determine which number is greater, equal to, or less. Every device from OP-AMP to ALU needs to perform comparison operations. At designing level, comparator can be designed by using different logic styles. Here, comparison is done for simple 4-Bit combinational comparator and cascaded comparator which we have designed …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 16–22 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Abstract: A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 38–41 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article
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Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Abstract: This paper describes a topology of voltage follower Class-AB Voltage Follower like Translinear voltage follower using MOS and DTMOS Transistor. The circuits are simulated in 90 nm technology. The results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. The analysis are made in terms of gain, bandwidth and transient response using ELDO spice, IC station and Design architect of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 64–70 Read article
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Design of 8 Bit High Speed Pipelined ADC
Abstract: High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in many electronic applications. The demand for high-speed, medium resolution, low power ADCs is satisfied by various ADC architectures like folding, flsubranging, pipeline etc. Of these, pipeline architecture has proven to be the most efficient for applications such as digital communication systems, data acquisition systems and video systems. Pipelined ADC offer attractive combination of high-speed, high-accuracy and low power consumption, which …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 71–80 Read article
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Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology
Abstract: A wide tuning range, low phase noise and low jitter 100 MHz Voltage-Controlled Oscillator (VCO) for DPLL was designed and implemented by 45 nm CMOS process technology using LT spice. There was a relation between the frequency tuning range, phase noise, and jitter at output of the VCO after linearizing the gain. Simulations using PTM 45 nm CMOS process technology shows, that a wide operation frequency range (tuning range) from …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 81–89 Read article
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A Review on Charge Pump Circuits for PLL Applications
Abstract: This paper presents a review on various architectures of charge pumps (CP) for high speed Phase-locked loop (PLL) applications. The different nonlinear marvels that influence the execution of PLL in view of the CPs circuit are examined. The various high performance CP circuits with reference voltage source, reference current source are analyzed that reduces the problems associated with the traditional charge pump circuit that consists leakage current, clock feed-through, charge …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 1–11 Read article
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All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey
Abstract: An all-digital phase locked loop (ADPLL) plays a great role in decreasing the development time of an application-specified integrated circuit (ASIC) products and helps to meet the time-to market requirement of product, because an ADPLL can be used as an IP core, so it is easily reusable in any design. Now a days ADPLL is being widely used in various fields such as control systems and digital communication systems. This …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 12–17 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology
Abstract: Low noise amplifier (LNA) is terribly important block in designing broadband receivers for wireless broadband communications. Being the primary active element in receiver chain it creates larger demand for LNAs that are smaller, consume less power, and provide sufficient gain, low noise and high compact design. The projected LNA is extremely integrated with low noise figure having wide calibration range with improved RF power handling system and acquires less space …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 37–44 Read article
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Memristor Modelling for Common Source Amplifier Using 180 nm Technology
Abstract: The objective of this research paper is on memristor modeling for common source amplifier circuit using cadence virtuoso tool at gpdk 180 nm technology. A memristor is the fourth element count after resistor, inductor and capacitor in fundamental electrical circuits assumption is proposed by Leon Chua, its characteristics is based on already occurred principles of voltages (V), current (I), flux (ᵩ) and charge (q). Ohm’s law states relation voltage to …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 45–54 Read article
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Design and Implementation of an Efficient Ternary Control Unit
Abstract: Multi-valued logic (MVL) is emerging as a thrust area of research due to several advantages offered by them over the conventional binary logic. Ternary logic is a promising alternative to the binary logic design technique thereby attracting a wide community of researchers to contribute in the design of ternary processor. The control unit is effectively the nerve center of a processor that plays a vital role in generating the appropriate …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 55–70 Read article
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Performance Analysis of DNA Sequencing Using Smith-Waterman Algorithm on FPGA
Abstract: The Smith-Waterman algorithm is the most accurate and optimal alignment algorithm for DNA sequencing. It is utilized to locate the ideal local alignment between two sequences. While looking sequence databases that may contain billions of sequences, this algorithm turns out to be computationally costly and tedious. Smith-Waterman algorithm needs additional memory space and this constrains the extent of a sequence to be aligned. In this study we will implement the …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 8–12 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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Power Reduction at 90 nm through Circuit Level Modification
Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article
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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell
Abstract: VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 73–77 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article