Recent Trends in Parallel Computing Review Article
Energy-Efficient Parallel Computing for Edge Devices: Techniques, Challenges, and Emerging Research Directions
Abstract
Edge computing brings computation closer to data sources, which supports low-latency applications but places substantial demands on energy-constrained and heterogeneous devices. Parallel execution across multicore CPUs, GPUs, FPGAs, and other accelerators can improve responsiveness, but it also complicates scheduling, power management, and resource allocation. This review examines six closely related technique families: energy-aware task scheduling, dynamic voltage and frequency scaling (DVFS), task offloading and resource allocation, artificial-intelligence-based optimization, hardware acceleration, and mathematical optimization. Representative studies show that energy efficiency is obtained through different mechanisms: battery-aware placement and scheduling, coordinated control of voltage and frequency, selective migration of computation, learned policies for dynamic environments, specialized data paths, and formal constrained optimization. Reported improvements are promising but are tied to particular devices, workloads, baselines, and measurement methods; therefore, they cannot be treated as directly comparable. The review also identifies recurring limitations, including limited hardware-level validation, weak cross-platform generalization of learning-based methods, inconsistent benchmarks, and fragmented optimization across system layers. Potential research directions include joint scheduling-DVFS-offloading control, hardware-software co-design, transfer learning, sparse-aware execution, federated optimization, energy-aware accelerators, and renewable-aware edge infrastructure. The central conclusion is that practical edge efficiency requires integrated policies that balance energy, latency, reliability, privacy, and implementation overhead rather than optimizing any single metric in isolation.
Keywords
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