1 publication

• Published Subscription 28 Aug 2018

  A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault

  By Ram Vishnu S, Yasodha T

  Abstract: Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach …

  Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 72–78 Read article →