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• Published Subscription 8 Aug 2019

  A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology

  By Vijayanand K, Sureshkumar N

  Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …

  Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article →