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Vemula Rajesh

Affiliation: Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu
Department: UG Student
Location: India

1 article

Published Subscription Review Article 5 May 2026
64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
By Sirigineedi Mounisha, Uppalapati Joshna Venkata Srujana, Vemula Rajesh, Velugubanti Lakshman, Yepuganti Manikanta, I.Rama Satya.Nageswara Rao, Saran Kumar

Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …

Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article