2 publications

• Published Subscription 13 Aug 2019

  Single Bit Low-Power High-Speed Full Adder

  By Sachin Pandurang Gaikwad, Sujatha Kondakinda, Harsh Upadhyay

  Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …

  Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article →

• Published Subscription 27 Dec 2017

  Single Bit Low-Power High-Speed Full Adder

  By Sachin Pandurang Gaikwad, Sujatha Kondakinda, Harsh Upadhyay

  Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …

  Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article →