2 publications

• Published Subscription 19 Aug 2019

  Low Power and High Speed Techniques for Sequential Circuits

  By shashank gautam

  Abstract: This paper proposes techniques like MT-CMOS, power gating, dual stack, Galeor and Lector to reduce the leakage power. A D-Flip Flop has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of D Flip Flop. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a …

  Published in Journal of Power Electronics and Power Systems · Vol. 4, Issue 3, 2014 · pp. 41–45 Read article →

• Published Subscription 9 Aug 2019

  Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy

  By shashank gautam, pramod sharma

  Abstract: The development of digital circuits, digital signal processors and other data processing integrated circuits, comparators are challenged by large area consumption. Comparator is most basic and fundamental component that performs comparison operation. This paper proposes a new approach to design an area efficient two bit magnitude comparator. Comparison is done on the grounds of area and power consumed between circuit designed by novel strategy and preexisting CMOS technique. The novel …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 1–6 Read article →