1 publication

• Published Subscription 9 Aug 2019

  Challenges Beyond 100 nm MOS Devices

  By savita maurya, sarita Shrivastava

  Abstract: MOS devices have been aggressively scaled down in research and in the production in last few years. Sub-100 nm feature size MOS circuits have been used for many. However, many serious limitations and problems emerged with such a small geometry MOSFETs are used to realize very large-scale integrated circuits. Commercial 45 nm technology node, has much higher production cost and it is one of the greatest concern for scaling down …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 1–4 Read article →