2 publications

• Published Subscription 9 Aug 2019

  Power Reduction at 90 nm through Circuit Level Modification

  By Angshuman Chakraborty, Sambhu Nath Pradhan

  Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …

  Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article →

• Published Subscription 19 Jul 2019

  A New High Speed Low Power 1 Bit Full Adder

  By Angshuman Chakraborty, Sambhu Nath Pradhan

  Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …

  Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article →