1 publication

• Published Subscription 5 Nov 2015

  FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier

  By Priyanka Rani, Sakshi Bajaj

  Abstract: This paper presents the hardware design of an IEEE P754-2008 complaint multiplier which works on binary integer decimal (BID) encoded decimal floating point numbers. This design uses a single binary multiplier with carry save feedback for both significant multiplication and rounding. It further uses the Dadda or Wallace tree structure to accumulate the partial products. In this design carry select adders, carry look ahead adders and ripple carry adders are …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 97–103 Read article →