1 publication

• Published Subscription 9 Aug 2019

  Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier

  By saguna goel, sakshi bajaj, amanpreet kaur

  Abstract: Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high-speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16 …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 7–14 Read article →