1 publication

• Published Subscription Original Research 26 Jun 2025

  Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations

  By Hardik Patel, Mitesh Limachia, Purvang Dalal, Sohilkumar Dabhi, Harshit Patel, Mitul Shah

  Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …

  Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article →