2 publications

• Published Subscription 6 Dec 2015

  Implementation of Sub Parts of SAR ADC

  By Purvi J Patel, Priyesh P Gandhi

  Abstract: This paper describes the implementation of different sub parts of SAR ADC using a 180 nm CMOS technology in Mentor Graphics Tool. There are mainly four blocks in the SAR ADC. They are sample and hold, dynamic latch comparator, SAR logic and DAC logic. The simulation results show the transient analysis waveforms of different blocks of SAR ADC. Here to reduce power consumption dynamic latch comparator is used. Here the …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 139–147 Read article →

• Published Subscription 6 Dec 2015

  Development of High Slew-Rate CMOS Operational-Amplifier

  By Chilka S Patel, Priyesh P Gandhi

  Abstract: In this paper operational-amplifier with high slew rate has been introduced. The simulation is carried out in 180 nm technologies. The supply voltage for 180 nm is 1.8 V. Different analysis for various characteristics of the operational amplifier such as gain, phase margin, slew rate, offset voltage and power dissipation is carried out in 180 nm CMOS technology. A current replicating branch with scaled-down transistors in combination with adaptive loads …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 128–131 Read article →