2 publications

• Published Subscription 13 Feb 2019

  Comparative Analysis of High Speed Comparator for A to D Converters

  By Priyesh Gandhi, Neha B. Rathod, N. M. Devashrayee

  Abstract: In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 4–10 Read article →

• Published Subscription 17 Mar 2018

  High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator

  By Priyesh Gandhi, N. M. Devashrayee

  Abstract: This paper comprises a novel fully differential double tail high performance comparators suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the requirement of high speed, low power consumption with low offset voltage. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in TSMC 180nm technology with ±0.9V supply. The proposed …

  Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 7–16 Read article →