STM Journals Peer-reviewed research from Consortium e-Learning Network

4 publications

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    System Level Modeling of ISMB Quadrature Transceiver

    By Narendra Bahadur Singh, rupam goswami, prashant singh

    Abstract: In this paper, a new ISMB quadrature transceiver system-level design architecture is presented along with its referenced mathematical models and these were verified using state-of-the-art system modeling tools. Unlike a K-TEK’s receiver, it does not suffer from the timing and template matching problems, and it circumvents processing at high frequencies, thereby reducing the on-chip circuit complexity and power consumption. Hilbert transform has been used at the output of the demodulator …

    Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 108–117 Read article

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    Low Power RF QPSK MODEM Design

    By Narendra Bahadur Singh, rupam goswami, prashant singh

    Abstract: System-level simulation including design of CMOS circuits for radio frequency QPSK MODEM targeting applications in 2.45 GHz industrial, scientific and medical (ISM) band has been presented in this paper. Based on the QPSK architecture, the MODEM consists of an analog mixer using a voltage multiplier, a 90 °phase shifter, delay circuits, a voltage adder and a filter to detect the information. A code reuse subsystem block consisting of Chebyshev filter …

    Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 75–86 Read article

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    High-speed CMOS ADCs Design

    By Narendra Bahadur Singh, prashant singh

    Abstract: This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. …

    Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 59–74 Read article

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    Decimator Design for Sigma-Delta ADC

    By Narendra Bahadur Singh, tripti sharma, prashant singh

    Abstract: This paper describes the design of a decimator which is used in digital signal processing as well as 10-bit sigma-delta analog-to-digital converter to down sample the incoming signal for further applications. It is also used for verification of the sigma-delta modulator functionality to reconstruct the incoming signal. The design has been carried out using 180 nm TSMC, CMOS foundry parameters for spice level 49 model parameters in TANNER EDA (Tspice). …

    Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 16–28 Read article

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