1 publication

• Published Subscription 10 Aug 2018

  Implementation and Analysis of Full Adder using low Power Adiabatic Techniques

  By Nidhi Vashist, Sambhavi .

  Abstract: AbstractIn this study, authors have discussed, designed and compared the low power adiabatic logic energy efficient recovery logic (ECRL) and positive feedback of adiabatic logic (PFAL) with conventional Complementary Mosfet (CMOS) logic. A one-bit full adder using these design techniques are implemented and results are compared like power, delay, transistor count and power delay product. Tanner tool v13 is used for designing of schematic and simulation. From the result, it …

  Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 1–8 Read article →