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Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor SizingBy sampath kumar, neerja singh
Abstract: With logical effort minimum delay of the path can be estimated by only knowing number of stages, path effort, and parasitic delay without the need to assign transistor sizes. This is superior to simulation where delay depends on sizes and you never achieve certainty that the size selected would offer minimum delay. In this work 3 cascaded inverters is being sized in the ratio 1:2:3 to achieve minimum propagation delay …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 29–31 Read article →