2 publications

• Published Subscription 9 Aug 2019

  Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog

  By ashima gandhi, neeraj kr. shukla

  Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article →

• Published Subscription 9 Aug 2019

  Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM

  By ashima gandhi, neeraj kr. shukla

  Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …

  Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article →