2 publications
-
Published Subscription
Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and PowerBy Vijay Savani, N. M. Devashrayee
Abstract: This paper presents the analysis and characterization of various topologies of dynamic latch based complementary metal oxide semiconductor (CMOS) comparator. Various comparator topologies like resistor divider comparator (RDC), differential pair comparator (DPC), double-tail dynamic latched comparator (DTDLC), energy efficient two-stage comparator (ETWC) and two-stage dynamic comparator (TSDL) are analyzed and compared for various performance parameters. Besides zero static power consumption, resistor divider comparator has high offset voltage and it depends …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 86–98 Read article →
-
Published Subscription
Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm TechnologyBy Vijay Savani, N. M. Devashrayee
Abstract: Paper describes the performance analysis, implementation and characterization of low-power and high-speed shared charge clocked-latch based comparator using 90-nm technology. There are two different topologies of the comparator viz. impedance dividing and differential current sensing comparators are combined to take the advantages and use their good features. The main focus of design is on improvement in speed by sharing charge and reduction in power dissipation. The topology is implemented in …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 20–26 Read article →